Digital Design Engineer

Qualcomm•San Diego, CA

3d•$115,600 - $173,400

About The Position

Qualcomm’s high speed parallel interfaces team is looking for a motivated and driven ASIC front end design engineer to work with a world class global team tasked to architect, design, and implement industry leading DDR and die-2-die interfaces fueling the company’s growth in high-speed compute, and server domains. The Digital Design Engineer will be responsible for designing, developing RTL, and implementing digital IPs serving the systems that connect SoC to DRAM devices and provide reliable high-speed link in multi-die systems. In this existing role you will work closely with systems architecture, verification, timing, and physical design engineers to design and implement control and data-path blocks for SoC interfaces. Ideal candidate will have experience on high speed, low power digital logic design development with hands on experience on ASIC front end implementation tool flow methodologies and silicon bring up. Expertise required on digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices and analysis, low power implementation and sign off, and gate level simulation debug. Position requires working closely with cross functional teams to enable all phases of implementation and Si bring up. Prior experience with high-speed parallel physical interfaces designs and low power designs is a plus.

Requirements

Bachelor’s Degree in Science, Engineering, or related field.
Minimum 4 years ASIC design, verification, or related work experience.
Expertise on digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices and analysis, low power implementation and sign off, and gate level simulation debug.

Nice To Haves

BS with 4 years or MS with 2 years relevant work experience
Experience on high speed, low power digital logic design with hands on experience on ASIC front end implementation tool flows and silicon bring up.
Expertise on digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices and analysis, low power implementation and sign off, design for test (DFT) flows for stuck and TDF modes, gate level simulation bring up and debug.
Working closely with cross functional teams in high paced and dynamic environment to enable all phases of implementation and Si bring up.
Prior experience with high-speed parallel physical interfaces designs and low power designs is a plus.

Responsibilities

Designing, developing RTL, and implementing digital IPs serving the systems that connect SoC to DRAM devices and provide reliable high-speed link in multi-die systems.
Working closely with systems architecture, verification, timing, and physical design engineers to design and implement control and data-path blocks for SoC interfaces.
Enabling all phases of implementation and Si bring up by working closely with cross-functional teams.