Responsible for design, verification, implementation (ASIC) for high-performance, physical layer, high speed wired data communication networks. Develop ASIC specification, architecture, and micro-architecture of major functional blocks in complex SOC solutions. Development/simulation of RTL hardware implementations in Verilog and System Verilog. Document and Execute verification plan. Analyze and improve design functionality with Lint, CDC and Power analysis. Participate and contribute in reviews. Work and communicate effectively with global team.
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Job Type
Full-time
Career Level
Entry Level
Education Level
No Education Listed