Digital Design Engineer Intern - Fall 2026
About The Position
As a Digital IC Design Engineer with Marvell, you’ll be a member of the Central Engineering business group. Marvell's Custom Compute Solutions business unit (CCSBU) develops cutting-edge semiconductor solutions in the most advanced technologies. Our focus is on solving the most difficult design problems in the areas of AI, data movement, memory/storage, switch, networking, security, and other infrastructure applications. You will be working alongside experienced engineers and interacting with architects, design, verification, and physical design engineers towards common team milestones. Marvell is committed to creating and fostering an inclusive, diverse, and engaging workplace where people feel fulfilled, inspired, and motivated to learn and grow both personally and professionally.
Requirements
- Must be currently enrolled in a university program working towards a BS/MS degree in Computer Engineering, Electrical Engineering, or equivalent degree
- Able to work collaboratively and independently, with initiative to pursue new and creative solutions
- Must have excellent written and verbal communication skills
- Working knowledge of Verilog or SystemVerilog hardware description languages
- Familiarity with digital electronics fundamentals
Responsibilities
- Perform circuit analysis of sub-circuit blocks across Process, Voltage, and Temperature (PVT) conditions to ensure designs meet performance, power, and area specifications.
- Under guidance from a technical mentor, iteratively analyze, debug, refine, and validate designs, documenting and summarizing results for cross-functional teams.
- Collaborate in a long-term, milestone-driven design cycle, using Cadence Virtuoso and Spectre X, Python/Perl scripting, and data analysis tools in a Linux environment to evaluate trade-offs and optimize complex digital designs.
- Design and develop RTL modules for logical blocks and functional units used within high-performance architectures.
- Define and influence block-level requirements to hit power, performance, and area targets for next-gen products.
- Handle multiple aspects of the ASIC design flow including RTL lint, block-level assertions, synthesis timing constraints, and timing closure.
- Collaborate and learn with a cross-functional team consisting of architects, designers, and verification engineers to solve technical issues.
Benefits
- Competitive compensation
- Great benefits
- Shared collaboration
- Transparency
- Inclusivity
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What This Job Offers
Job Type
Full-time
Career Level
Intern
