Design Engineer II

Silicon Laboratories•Austin, TX

2d•Hybrid

About The Position

As a Digital Design Engineer II, you will develop highly integrated, low-power System-on-Chip (SoC) devices for the IoT wireless market. The role involves SoC architecture and integration, RTL design, synthesis and analysis, pre-silicon verification, and silicon validation and bring-up. You will collaborate with technical staff and cross-functional teams throughout the development lifecycle to optimize designs for customer scenarios and power, performance, and area.

Requirements

Master’s degree in Electrical Engineering.
3–5 years of professional experience in digital CMOS IC design.
Verilog RTL design experience, including taking designs through the silicon development lifecycle to production.
Knowledge of embedded processor systems and C coding.
Experience with logic simulators for RTL and gate-level simulation, design and waveform browsers, and power analysis tools.
Experience with logic synthesis and timing constraints.
Experience working with analog and mixed-signal designs to support their integration and verification in SoCs.
Experience with scripting and automation; knowledge of Python, Perl, and Tcl.
Experience with revision control and configuration management systems such as Perforce, Git, or Methodics.
Excellent written and verbal communication skills.
Demonstrated ability to produce high output in a self-driven manner.
Experience with AI-powered tools and technologies used to enhance productivity, analysis, and decision-making.

Responsibilities

Develop complex SoC and chip architectures containing multiple processors, digital and mixed-signal subsystems, and multiple power and clock domains, optimizing power for customer scenarios.
Design RTL modules using SystemVerilog HDL and adhere to quality standards.
Prepare and conduct architecture, design, and verification reviews with technical staff throughout the project lifecycle.
Configure and integrate digital and mixed-signal IPs at the SoC level, including processors, memory and controllers, buses, power and clocking systems, security systems, machine learning, radio systems, analog IP, and pads.
Perform logic synthesis and full-chip timing and power analysis to optimize designs for customer scenarios.
Work with the backend team to optimize designs for power, performance, and area.
Perform pre-silicon verification using a combination of block- and chip-level test benches.
Validate and bring up designs on silicon, supporting cross-functional teams.

Benefits

Medical plans, including a choice of PPO or Consumer Driven Health Plan with HSA
Dental insurance
Vision insurance
401(k) plan with match and Roth plan option
Equity rewards (RSUs)
Life and AD&D coverage
Disability coverage
Flexible spending accounts
Adoption assistance
Backup childcare
Commuter benefits
Legal benefits
Pet insurance
Flexible PTO schedule
Three paid volunteer days per year
Charitable contribution match
Tuition reimbursement
Free downtown parking
Onsite gym
Monthly wellness offerings
Free snacks
Annual cash bonus may be included in the total compensation package