Sr. Digital ASIC Design Engineer (TERADYNE, Agoura Hills, CA)

Teradyne•Agoura Hills, CA

6d•$154,900 - $247,800•Onsite

About The Position

Teradyne's Digital ASIC Group is seeking a Senior Digital ASIC Design Engineer to join our engineering team in Agoura Hills, California. In this role, you will contribute to the architecture, design, implementation, and validation of complex digital subsystems used in next-generation mixed-signal ASICs for semiconductor test applications. Working closely with system architects, analog designers, verification engineers, and physical design teams, you will take ownership of critical RTL design activities from concept through silicon bring-up. You will be responsible for delivering robust, high-quality digital designs that achieve performance, power, area, and reliability targets while supporting first-pass silicon success.

Requirements

BSEE required; MSEE preferred in Electrical Engineering, Computer Engineering, or a related field.
8+ years of digital ASIC or SoC design experience.
Strong RTL design expertise using Verilog and/or SystemVerilog.
Experience designing complex digital logic including: State machines, FIFOs and buffering architectures, High-speed datapathes, Arbitration and control logic, Clocking and reset architectures.
Solid understanding of ASIC development flows, including: Logic synthesis, Static Timing Analysis (STA), Clock Domain Crossing (CDC), Timing closure.
Experience developing and integrating third-party and custom IP into large-scale ASICs or SoCs.
Strong debugging and problem-solving skills throughout the design lifecycle.
Proficiency with scripting and automation tools such as Python, Tcl, Perl, or Make.

Nice To Haves

Experience with mixed-signal ASIC development and collaboration with analog design teams.
Knowledge of Design-for-Test (DFT), scan insertion, and MBIST methodologies.
Experience supporting silicon bring-up, validation, and characterization activities.
Familiarity with UVM-based verification environments and simulation/debug tools.
Experience working on advanced process nodes and high-performance semiconductor products.

Responsibilities

Contribute to the architecture, design, implementation, and validation of complex digital subsystems used in next-generation mixed-signal ASICs for semiconductor test applications.
Take ownership of critical RTL design activities from concept through silicon bring-up.
Deliver robust, high-quality digital designs that achieve performance, power, area, and reliability targets.
Support first-pass silicon success.
Drive technical solutions in a collaborative, cross-functional environment.
Continuously improve design methodologies, automation, and engineering efficiency.
Take a proactive approach to problem solving and ownership of deliverables from specification through production release.