Digital ASIC Design Engineer

Qualcomm • San Diego, CA

3d

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.
Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills. This is a great opportunity to join a fast-paced SoC team responsible for RTL Design, flows and methodology for high performance ASICs in sub-4nm process for mobile, automotive, compute, AI and XR space
An ideal candidate will oversee definition, design, verification, and documentation for ASIC development for a variety of products. Determines architecture design, logic design, and system simulation. Provides technical expertise for next generation initiatives.

Requirements

• Bachelor's degree in Science, Engineering, or related field
• RTL design experience with Verilog/System Verilog or VHDL
• Proficiency in any automation/scripting language such as Python/Perl
• Bachelor's degree in Science, Engineering, or related field.

Nice To Haves

• Master's degree in Electrical Engineering, Computer Science, or Computer Engineering.
• 6+ months of relevant experience in ASIC design, scripting, architecture
• Specific experience in clock design of ASIC/SOC

Responsibilities

• Uses tools/applications to execute the architecture and design of SOC according to design protocol provided.
• Resolves architecture, design, or verification problems by applying sound ASIC engineering practices with some supervision.
• Executes the design and supports verification efforts of ASICs, SoC, and IP cores or own specific assigned part of a block with supervision from project lead with focus on clock/power related features
• Participate in the design and analyses of IPs
• Identify areas for flow and process improvements
• Feedback silicon learnings to improve design methodology, IP, SoC design

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level
• Number of Employees: 5,001-10,000 employees