Senior Digital ASIC Design Engineer
About The Position
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. Ciena’s WaveLogic products are central to advancing high-performance optical networking solutions. This role contributes to the design and integration of next-generation ASIC technologies that power critical telecommunications infrastructure. The position enables delivery of scalable and high-quality silicon solutions through cross-functional collaboration.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science
- 5+ years of experience in ASIC design.
- Ability to work independently while contributing within a team environment
- Application of structured approaches to solving complex technical problems
- Written and verbal communication in English within technical environments
- Utilization of Verilog, SystemVerilog, and Python in digital design workflows
- Application of digital design concepts including synthesis, static timing analysis (STA), timing closure, and asynchronous clock domain crossing
Nice To Haves
- Exposure to programming languages including C, C++, and SystemC
- Use of scripting or object-oriented programming approaches in engineering workflows
- Experience with ASIC verification.
Responsibilities
- Contribute to top-level ASIC design and integration for WaveLogic products
- Interpret architecture and functional specifications and collaborate with systems engineers and architects
- Develop and assemble top-level RTL designs integrating multiple IP blocks
- Maintain and enhance technology-specific libraries for advanced semiconductor nodes
- Own and manage tool flows supporting ASIC top-level integration
- Create timing constraints and analyze synthesis, timing, layout, and backend reports
- Perform lab validation of ASIC prototypes and production silicon
Benefits
- medical
- dental
- vision plans
- participation in 401(K) (USA) & DCPP (Canada) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company-paid holidays
- paid sick leave
- vacation time
- Paid Family Leave
- other leaves of absence
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What This Job Offers
Job Type
Full-time
Career Level
Senior
