DFT Principial Engineer

American IT Systems • Santa Clarita, CA

7d

About The Position

This role focuses on DFT (Design for Testability) engineering, specifically involving scan insertion, ATPG (Automatic Test Pattern Generation), and MBIST (Memory Built-In Self-Test). The engineer will be responsible for scan insertion, ATPG, and validation for SOCs (System on Chips).

Requirements

• 8 to 12 yrs experience in Scan Insertion, ATPG, MBIST
• Scan insertion, ATPG Validation for SOC
• Experience with Tessent and Modus for stuck-at and transition (at-speed) fault models, including coverage analysis and test point insertion
• Experience on SGDFT, Coverage Analysis & Improvement on SCAN, ATPG, Scan insertion(Quick Synth flow using FC), Standalone Scan insertion flow using DC, MBIST insertion
• Good hands-on experience with ATPG GLS(ZD +SDF) simulation debugs
• Working experience on SSN Pattern Retarget & FC/SOC GLS validation
• Experience of working in Intel environment

Responsibilities

• Scan insertion
• ATPG
• MBIST
• ATPG Validation for SOC
• Test point insertion
• SGDFT
• Coverage Analysis & Improvement on SCAN, ATPG, Scan insertion
• Standalone Scan insertion flow using DC
• MBIST insertion
• ATPG GLS(ZD +SDF) simulation debugs
• SSN Pattern Retarget & FC/SOC GLS validation

What This Job Offers

• Career Level: Principal
• Education Level: No Education Listed