DFT Methodology Engineer

NVIDIA•Santa Clara, CA

3d•$168,000 - $310,500

About The Position

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

Requirements

Master’s degree (or equivalent experience) in Electrical Engineering or related field with proven experience in DFT or related domains.
10+ years of hands-on experience in SoC architecture, RTL design, and verification.
Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools.
Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs.
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges.

Nice To Haves

Knowledge of DFT security and hardware system security is a plus.

Responsibilities

Own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, scan and memory dump and DFX security methodology.
Help architect, develop and deploy DFT methodologies for our next generation products including RTL design, Verification, pattern generation, partnering with teams like timing, physical design, software, bringup, production.
Help mentor junior engineers on test designs and trade-offs including cost and quality.