DFT Methodology Engineer

NVIDIA • Us, CA

1d

About The Position

DFT Methodology Engineer at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. The role involves owning and working with cross-functional teams to implement state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, scan and memory dump and DFX security methodology. Additionally, the engineer will help architect, develop and deploy DFT methodologies for next-generation products, including RTL design, verification, pattern generation, and partnering with teams like timing, physical design, software, bringup, and production. The role also includes mentoring junior engineers on test designs and trade-offs.

Requirements

• Master’s degree (or equivalent experience) in Electrical Engineering or related field with proven experience in DFT or related domains.
• 10+ years of hands-on experience in SoC architecture, RTL design, and verification.
• Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools.
• Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs.
• Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
• Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges.

Nice To Haves

• Knowledge of DFT security and hardware system security is a plus.

Responsibilities

• Implement state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, scan and memory dump and DFX security methodology.
• Architect, develop and deploy DFT methodologies for next-generation products.
• Partner with teams like timing, physical design, software, bringup, and production.
• Mentor junior engineers on test designs and trade-offs including cost and quality.
• Work with cross-functional teams on RTL design, verification, and pattern generation.

Benefits

• Highly competitive salaries
• Comprehensive benefits package
• Equity
• Benefits

What This Job Offers

• Job Type: Full-time
• Career Level: Senior