DFT Engineer

Wipro • Mountain View, CA

11h

About The Position

We are seeking a DFT Engineer with hands-on experience in Scan, MBIST, ATPG generation, and pattern simulation for complex SoC/IP designs. Key Responsibilities Develop and implement Design-for-Test (DFT) architecture for IPs and SoCs. Perform Scan insertion and Scan chain verification. Integrate and validate MBIST solutions for embedded memories. Generate ATPG patterns for stuck-at, transition, and other manufacturing fault models. Execute ATPG simulation and pattern verification to ensure coverage and pattern quality. Analyze and improve fault coverage while reducing pattern count. Debug DFT-related issues during implementation and verification. Collaborate with RTL, Physical Design, Verification, and Test Engineering teams. Support silicon bring-up and production test activities when required.

Requirements

• Strong understanding of DFT fundamentals.
• Hands-on experience in: Scan Architecture, Scan Insertion, Scan Compression, MBIST Integration, ATPG Pattern Generation, ATPG Simulation, Fault Coverage Analysis, DFT Verification
• Experience with industry-standard DFT tools such as: Tessent, Synopsys DFT Compiler, TetraMAX / TestMAX ATPG
• Good knowledge of Verilog/SystemVerilog and simulation environments.
• Familiarity with manufacturing test concepts and silicon debug.
• VLSI Design For Testability - DFT
• 8-10 Years experience

Nice To Haves

• Experience with large SoC or CPU/GPU designs.
• Knowledge of IJTAG, Boundary Scan (JTAG), LBIST, and Test Compression.
• Experience supporting post-silicon test and yield improvement activities.
• Modus (preferred)

Responsibilities

• Develop and implement Design-for-Test (DFT) architecture for IPs and SoCs.
• Perform Scan insertion and Scan chain verification.
• Integrate and validate MBIST solutions for embedded memories.
• Generate ATPG patterns for stuck-at, transition, and other manufacturing fault models.
• Execute ATPG simulation and pattern verification to ensure coverage and pattern quality.
• Analyze and improve fault coverage while reducing pattern count.
• Debug DFT-related issues during implementation and verification.
• Collaborate with RTL, Physical Design, Verification, and Test Engineering teams.
• Support silicon bring-up and production test activities when required.

Benefits

• full range of medical and dental benefits options
• disability insurance
• paid time off (inclusive of sick leave)
• other paid and unpaid leave options

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed