Design Verification, Forward Deployed Engineering

OpenAI • San Francisco, CA

1d

About The Position

OpenAI’s Forward Deployed Engineering team partners with leading semiconductor companies to deploy production-grade AI systems across the entire chip design lifecycle: design, verification, and physical design. We operate at the intersection of customer delivery and core platform development, embedding deeply with customers to translate frontier model capabilities into systems that materially reduce design cycles, improve verification quality, and accelerate innovation. Our work turns early, high-touch deployments into reusable solution patterns, evaluation practices, and technical playbooks that scale across the semiconductor ecosystem. We are seeking an experienced Design Verification Engineer to join our semiconductor-focused Forward Deployed Engineering team. This is an IC role that will begin with a strong emphasis on design verification expertise, evaluation curation, and technical leverage across deployments, with the expectation that the person will grow into a broader Forward Deployed Engineering role over time. In the near term, you will serve as a senior technical SME for verification workflows: helping FDEs, Product, and Research teams understand how DV work is done in practice, pressure-testing AI-assisted verification ideas against real engineering workflows, and raising the quality of our solutions through deep domain judgment. You will help the broader team build fluency in verification methodology, tooling, and trade-offs. Over time, we expect this role to expand beyond SME support into broader FDE ownership: partnering directly with customers, shaping deployment strategy, building and iterating production-grade AI systems, driving technical workstreams, and helping turn high-touch semiconductor deployments into repeatable solutions. This is a strong fit for someone who brings deep design verification expertise today and is excited to grow into a customer-facing, systems-building, delivery-oriented FDE role.

Requirements

• BS/MS in EE, CE, CS, or equivalent with 5+ years of experience in design verification for complex IP, subsystem, or SoC programs
• Demonstrated success verifying complex hardware systems in industry-standard flows, with deep familiarity in block-, subsystem-, and/or top-level verification methodologies
• Strong hands-on expertise in SystemVerilog, UVM, and common simulation/debug tools such as VCS, Questa, Verdi, or equivalent
• Strong understanding of constrained-random verification, directed testing, scoreboards, checkers, monitors, stimulus generation, regression infrastructure, and coverage analysis
• Strong knowledge of computer architecture, RTL/microarchitecture, memory systems, coherency, interconnects, and verification methodology
• Experience defining verification plans, triaging bugs, and driving debug and root-cause analysis in close partnership with design teams
• Strong scripting and automation skills in Python or similar; experience building verification tooling, harnesses, or workflow automation is a plus
• Comfortable operating as a consultative expert who can shape technical direction, evaluate solution quality, and raise the bar across multiple deployments
• Excited to grow beyond domain SME responsibilities into a broader Forward Deployed Engineering role, including hands-on solution building, customer-facing delivery, and ownership of deployment outcomes

Nice To Haves

• Experience across multiple semiconductor companies, design environments, or tool stacks, with a point of view shaped by different verification cultures and methodologies
• Familiarity with adjacent domains such as RTL design, formal verification, emulation, performance analysis, or physical design
• Experience applying AI/LLM systems to semiconductor workflows
• Experience creating reusable evals, methodology assets, or technical playbooks
• Prior experience in customer-facing, consultative, field engineering, solutions engineering, or technical delivery roles

Responsibilities

• Serve as the design verification SME for semiconductor deployments, helping teams reason about verification workflows across block, subsystem, and SoC environments
• Shape AI-assisted workflows for test generation, regression triage, debug, root-cause analysis, and coverage closure
• Curate evaluations with FDEs and customer SMEs, including golden tasks, labeled examples, rubrics, acceptance criteria, and realistic benchmarks grounded in solved issues and real engineering workflows
• Build lightweight prototypes, eval harnesses, and tooling that validate opportunities and improve solution quality
• Educate and mentor the broader FDE team on verification concepts, tooling, and methodology so the org can engage semiconductor workflows with greater depth and confidence
• Partner with FDEs during customer discovery and scoping to translate ambiguous pain points into clear solution hypotheses, success criteria, and technical plans
• Support customer-facing technical conversations as a trusted advisor, engaging credibly with technical leaders
• Progressively take on broader FDE responsibilities, including customer discovery, solution architecture, prototype development, production deployment, and ownership of technical workstreams

Benefits

• We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.
• Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates.
• We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree