Design Verification Engineer

Apple•Cupertino, CA

6d•Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA.

Requirements

Using hardware description languages like Verilog to develop testbenches, reference models, understand, verify and debug digital designs.
Implementing programming languages like C/C++, object-oriented programming to work with system models, design reference models, stimulus drivers that need object-oriented concepts.
Using combinational and sequential circuits designs to understand, verify and debug digital designs.
Understanding of Microprocessors architecture, processor organization, instruction set architecture to work on microprocessor design verification, integration and debug.
Understanding advanced computer architecture concepts to work on CPU integration and verification.
Knowledge of Microelectronics and semiconductor physics to work on digital and mixed-signal models, integration, debug.
Understanding of computer networking, design of communication protocols and wireless networks to work on design of reference models and verification of wireless chips.
Understanding of parallel computing to work on multi-threaded design, stimulus generation and using mutex, semaphore and parallel computing concepts.
Using Unix/Linux operating system to execute on all job functions including file management, system monitoring, automation through scripting.
Using scripting languages such as Python to work on system testbenches and automate verification flows.

Responsibilities

Understand details of High-Efficiency SOC Architecture, standard SOC peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe, DDR, Memory Controller Sub Systems, USB, PLL, power-up, Secured Boot schemes.
Create coverage driven verification plans from specifications, review and refine to achieve coverage targets.
Create IP level module and sub-system verification plan, TB, portable test benches, sequences, and test infrastructure.
Architect highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches, and test suites to SOC level, achieve targeted coverage, working with design, architecture, SW, FW, and external IP delivery teams to efficiently integrate and verify overall SOC design.
Work closely with DV methodology architects to improve verification flow.