Design Verification (DV) Engineer

DensityAI•Mountain View, CA

12d•$200,000 - $320,000•Remote

About The Position

This role involves owning the functional verification of a custom AI accelerator's digital logic. The responsibilities include writing testbenches, building verification environments, debugging waveforms, and driving coverage closure. The work will be done using SystemVerilog and UVM with industry-standard simulators like Synopsys VCS and Cadence Xcelium, and waveform viewers such as Synopsys Verdi. The primary goal is to ensure the design's correctness before tape-out, preventing costly silicon defects.

Requirements

SystemVerilog: expert-level proficiency in both RTL reading and verification constructs (classes, interfaces, constraints, covergroups).
UVM: experience building or significantly extending UVM environments, understanding agents, sequences, scoreboards, and the factory pattern.
Logic simulation: hands-on experience with Synopsys VCS, Cadence Xcelium, or equivalent, with the ability to debug simulation failures efficiently.
Waveform debugging: proficiency with Synopsys Verdi, Cadence SimVision, or equivalent, with the ability to trace signal transitions and isolate issues.
Verification methodology: understanding of coverage-driven verification, constrained-random testing, and building a verification plan.

Nice To Haves

Formal verification experience (property checking, model checking).
SVA assertion writing for protocol and microarchitectural properties.
Coverage analysis and closure experience on a tape-out project.
Python or Tcl scripting for regression automation and log parsing.
RISC-V ISA familiarity.
Experience verifying processor or accelerator designs specifically.

Responsibilities

Build the UVM verification environment for the custom accelerator, including developing the testbench architecture, constrained-random stimulus generators, scoreboards, and coverage models.
Write directed and constrained-random tests targeting compute pipeline, NOC routing, memory subsystem, and control plane logic.
Debug RTL mismatches using waveform analysis in Verdi/DVE, isolating root causes and filing clear bug reports.
Drive functional coverage closure by defining coverage goals, tracking progress, and identifying verification holes.
Develop assertion-based verification (SVA) monitors for protocol compliance (APB, AXI, SPI, JTAG interfaces).
Validate ISA-level correctness to ensure the LLVM backend's generated code executes correctly on the RTL design.
Establish regression infrastructure, including automated nightly runs, pass/fail reporting, and coverage merging.