Design Verification Engineer

Altera•San Jose, CA

1d•$100,000 - $120,000•Onsite

About The Position

As a Design Verification Engineer at Altera, you will play a key role in ensuring the functional correctness and quality of next-generation FPGA and SoC products. You will develop and execute comprehensive verification strategies for complex digital designs, collaborating closely with architecture, RTL design, physical design, firmware, and software teams throughout the product development lifecycle. This position offers the opportunity to work on cutting-edge programmable logic technologies while leveraging industry-leading verification methodologies, constrained-random verification, coverage-driven verification, and assertion-based verification to deliver world-class semiconductor products.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline with 4+ years of industry experience in digital design verification, ASIC verification, FPGA verification, or SoC verification.
4+ years of experience verifying digital ASIC, FPGA, or SoC designs using SystemVerilog and Universal Verification Methodology (UVM).
4+ years of experience developing constrained-random and directed verification testbenches for complex digital designs.
3+ years of experience writing SystemVerilog Assertions (SVA) and applying assertion-based verification methodologies.
3+ years of experience using industry-standard simulation tools such as Synopsys VCS, Cadence Xcelium, Siemens QuestaSim, or equivalent simulators.
3+ years of experience debugging RTL functional issues using waveform analysis, simulation debugging tools, and verification methodologies.
3+ years of experience developing verification components including UVM agents, drivers, monitors, scoreboards, sequences, and functional coverage models.
3+ years of experience analyzing functional coverage, code coverage, assertion coverage, and coverage closure metrics.
2+ years of experience using scripting languages such as Python, Perl, Tcl, Shell, or similar languages to automate verification workflows and regression environments.
2+ years of experience using revision control systems such as Git, Perforce, or equivalent version control tools.
2+ years of experience collaborating with RTL design, architecture, physical design, firmware, or software engineering teams throughout the product development lifecycle.
1+ year of experience developing automated regression environments and analyzing regression results to improve verification quality and productivity.
1+ year of experience verifying one or more high-speed digital interfaces such as PCIe, Ethernet, DDR, LPDDR, HBM, AXI, AMBA, USB, CXL, or similar industry-standard protocols.
Applicants must be eligible for any required U.S. export authorizations.

Nice To Haves

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
6+ years of experience in ASIC, FPGA, or SoC design verification.
Experience verifying complex FPGA architectures, programmable logic devices, or configurable hardware systems.
Experience verifying high-speed interfaces including PCIe Gen4/Gen5, Ethernet, DDR4/DDR5, LPDDR, HBM, CXL, or SerDes protocols.
Experience with formal verification tools and methodologies.
Experience with hardware emulation platforms, FPGA prototyping, or acceleration-based verification.
Experience developing reusable verification IP (VIP) for complex semiconductor products.
Experience with low-power verification methodologies including UPF, CPF, retention, isolation, and power-aware simulation.
Experience using lint, CDC, RDC, or static verification tools.
Experience with post-silicon validation, silicon bring-up, or hardware/software co-verification.
Experience applying coverage-driven verification methodologies to large-scale ASIC or FPGA programs.

Responsibilities

Develop and execute block-level and subsystem-level verification plans for complex FPGA and SoC designs.
Create reusable SystemVerilog and UVM-based verification environments, agents, sequences, scoreboards, and checkers.
Develop constrained-random and directed test cases to verify digital logic functionality and achieve functional coverage goals.
Create and maintain assertions using SystemVerilog Assertions (SVA) to improve design quality and identify functional issues early.
Debug simulation failures, functional bugs, and RTL issues by working closely with RTL designers, architects, and firmware engineers.
Perform coverage analysis including functional, code, toggle, and assertion coverage to ensure verification completeness.
Develop verification infrastructure, automation, and regression environments to improve engineering productivity.
Participate in design reviews, verification reviews, and bug triage meetings throughout the development lifecycle.
Collaborate with emulation, FPGA prototyping, post-silicon validation, and software teams to support product bring-up and validation.
Contribute to continuous improvement of verification methodologies, reusable verification IP, and engineering best practices.