Design Verification Architect

Intel Corporation•Folsom, CA

2d•$164,470 - $232,190•Hybrid

About The Position

Defines, architects, and documents verification strategy and methodologies for implementing and verifying the pre-silicon design in the most optimal manner. Architects testbenches and develops Universal Verification Methodology (UVM) or formal-based verification approaches. Integrates block testbenches in chip-level UVM environments and verifies integration.

Requirements

Bachelor's degree with 10+ years of relevant industry experience, or a Master's degree in a related field with 8+ years of relevant industry experience
8+ years of experience with/in: IP/SoC pre-silicon validation and coding using SystemVerilog
8+ years of experience with/in: Hardware simulation tools and methodologies (VCS/Verdi)
8+ years of experience with/in: IP environment and configuration management tools
8+ years of experience with/in: UVM methodology

Nice To Haves

Demonstrated ability to debug complex logic designs and validate system-level functionality
DDR design domain knowledge with strong understanding of DFI/DDR/LPDDR protocols
Experience with VSCode, GitHub Copilot, or any other AI-assisted development tools
Experience to Formal Property Verification and Git version control

Responsibilities

Define, architect, and document verification strategy and methodologies for implementing and verifying pre-silicon design in the most optimal manner
Architect testbenches and develop Universal Verification Methodology (UVM) or formal-based verification approaches
Integrate block testbenches in chip-level UVM environments and verify integration
Develop test strategy, testbench architecture, and test plans for design blocks to conform to specifications
Enable interaction with analog and digital teams and support post-silicon validation activities
Collaborate with architecture and design teams to create random test generation plans, run functional simulations to identify gaps in design specifications, and conduct failure analysis, coverage analysis, and closure
Define and develop the security validation strategy and validation infrastructure to incorporate security tools and methods to improve security coverage