Design Validation & Test (DVT) Engineer (multiple roles/openings)

Celero Communications•Irvine, CA

5d•Onsite

About The Position

Celero is hiring Junior, Senior, and Principal Design Validation & Test (DVT) Engineers in Irvine, California. The role focuses on post-silicon validation and characterization of next-generation coherent DSP ASICs for AI and hyperscale optical networking. Engineers will support first-silicon bring-up through production release, validate product readiness for customer deployment and high-volume production, and work cross-functionally with Architecture, RTL Design, Firmware, Systems, Product Engineering, and customers. The position offers the opportunity to shape validation strategy, define best practices, and build validation infrastructure in a fast-paced startup environment. The posting describes the Principal-level role as a technical leadership position. Responsibilities include creating validation plans, debugging hardware, firmware, RTL, and system issues, building Python automation, characterizing silicon, supporting customer engagements, and documenting results. The role is onsite at Celero’s Irvine, California headquarters.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
8+ years of hands-on post-silicon validation, DVT, or silicon bring-up experience with complex ASICs or SoCs.
Experience bringing first silicon to production in networking, communications, data center, AI, or high-performance computing products.
Strong understanding of silicon debug methodologies and structured root-cause analysis.
Extensive experience with laboratory equipment such as oscilloscopes, BERTs, protocol analyzers, network analyzers, and logic analyzers.
Strong knowledge of one or more high-speed protocols, such as PCIe, Ethernet, SerDes, CXL, USB, SPI, or I²C.
Strong Python programming skills for automation, regression development, and data analysis.
Experience validating firmware, embedded software, drivers, and hardware/software interfaces.
Ability to interpret schematics and understand board design, power sequencing, signal integrity, and hardware debug.
Excellent communication skills and ability to work across engineering and customer teams.
Comfort working in a fast-paced startup where priorities evolve and team members have significant technical ownership.
Ability to work onsite at Celero’s Irvine, California headquarters.

Nice To Haves

Experience validating coherent optical DSPs, networking ASICs, Ethernet switch silicon, AI accelerators, GPUs, storage controllers, or high-speed communications devices.
Strong knowledge of Ethernet, PCIe, OIF, IEEE, or related compliance specifications.
Experience with PIPE, PCS, PMA, MAC, PHY, or other physical and protocol layers of high-speed interfaces.
Experience building scalable validation automation, regression systems, dashboards, and data pipelines.
Familiarity with customer platform validation and hyperscale qualification processes.
Experience mentoring engineers and leading technical initiatives across multiple engineering disciplines.

Responsibilities

Lead post-silicon validation and characterization of ASICs and SoCs from first silicon through production release.
Develop validation plans covering functionality, performance, interoperability, compliance, stress testing, corner cases, and reliability.
Enable first-silicon bring-up using JTAG, scan, embedded debug features, and board-level diagnostics.
Validate high-speed interfaces and industry-standard protocols, including PCIe, Ethernet, SerDes, CXL, SPI, I²C, and MDIO.
Use laboratory equipment to validate and characterize silicon.
Debug hardware, firmware, RTL, and system-level issues with cross-functional engineering teams; identify root causes and drive resolution.
Develop Python-based automation for test execution, regression, silicon characterization, data analysis, and reporting.
Validate firmware, bootloaders, device drivers, and hardware/software interfaces across platforms.
Characterize silicon performance, power, thermal behavior, margins, and compliance against architectural specifications.
Lead debug reviews and provide technical direction on validation methodology, infrastructure, and best practices.
Support early customer engagements by reproducing and resolving system-level issues in collaboration with applications engineering.
Document validation results, silicon characterization data, debug findings, and production-readiness reports.