Design for Test Engineer

Apple • Cupertino, CA

4d • $146,717 - $218,000 • Hybrid

About The Position

Apple is seeking a Design for Test (DFT) Engineer to develop and implement DFT architecture and specifications. This role involves creating DFT infrastructure, coding Verilog RTL for DFT logic, and collaborating with designers for integration and checks. The engineer will partner with designers on Static Timing Analysis (STA), physical, power, and logical issues, and coordinate with the Design Verification (DV) team to verify DFT implementations. Responsibilities include generating Automatic Test Pattern Generation (ATPG) vectors, analyzing test coverage, supporting Test Time Reduction (TTR) and silicon diagnosis, and managing schedules for multi-functional engineering efforts. The position is 40 hours/week and is available in Cupertino, California, and various unanticipated locations throughout the USA.

Requirements

• Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation.
• Designing and verifying RTL using Verilog hardware description language.
• Knowledge of MBIST, march algorithms and memory fault models.
• Designing Joint Test Action Group (JTAG) architecture and programming DFT control registers for chip testing.
• Automating DFT design flows using Python or Perl scripting languages.
• Knowledge of STA for timing analysis.
• Running RTL and gate-level simulations using industry-standard tools such as VCS or NCSIM to debug and resolve design issues.
• Utilizing ATPG tools for scan pattern generation and fault coverage analysis across various fault models.
• Performing silicon failure diagnosis and analysis from Automated Test Equipment (ATE) to improve yield and manufacturing processes.
• Applying low-power design techniques to reduce overall chip power consumption.

Responsibilities

• Develop and implement DFT architecture and document DFT specifications.
• Implement DFT infrastructure.
• Code Verilog Register Transfer Language (RTL) for DFT logic.
• Collaborate with designers to integrate DFT implementations and run various checks.
• Partner with designers on STA, physical, power and logical issues.
• Coordinate with DV team to verify DFT implementations in RTL and Gate level, review verification coverage and implement ECOs.
• Generate ATPG structural test vectors and analyze and improve test coverage.
• Engage with test engineers to debug and bring up test vectors on silicon.
• Support TTR and silicon diagnosis efforts.
• Handle schedules and support multi-functional engineering efforts.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• A range of discounted products and free services
• Reimbursement for certain educational expenses — including tuition
• Discretionary bonuses or commission payments
• Relocation assistance
• Opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs
• Discretionary restricted stock unit awards
• Purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan

What This Job Offers

• Job Type: Full-time
• Career Level: Senior