Design for Test Engineer

Apple•Cupertino, CA

3d•Hybrid

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA.

Requirements

Designing and verifying RTL using Verilog hardware description language.
Knowledge of MBIST, march algorithms and memory fault models.
Designing Joint Test Action Group (JTAG) architecture and programming DFT control registers for chip testing
Automating DFT design flows using Python or Perl scripting languages
Knowledge of STA for timing analysis.
Running RTL and gate-level simulations using industry-standard tools such as VCS or NCSIM to debug and resolve design issues
Utilizing Automatic Test Pattern Generation (ATPG) tools for scan pattern generation and fault coverage analysis across various fault models
Performing silicon failure diagnosis and analysis from Automated Test Equipment (ATE) to improve yield and manufacturing processes
Applying low-power design techniques to reduce overall chip power consumption

Responsibilities

Develop and implement DFT (Design For Test) architecture and document DFT specifications.
Implement DFT infrastructure.
Code Verilog Register Transfer Language (RTL) for DFT logic.
Collaborate with designers to integrate DFT implementations and run various checks.
Partner with designers on STA (Static Timing Analysis), physical, power and logical issues.
Coordinate with DV (Design Verification) team to verify DFT implementations in RTL and Gate level, review verification coverage and implement ECOs (Engineering Change Orders).
Generate ATPG (Automatic Test Patten Generation) structural test vectors and analyze and improve test coverage.
Engage with test engineers to debug and bring up test vectors on silicon.
Support TTR (Test time Reduction) and silicon diagnosis efforts.
Handle schedules and support multi-functional engineering efforts.