This role involves Design For Test (DFT) implementation for 3nm and 5nm Networking chips, as well as IP DFT work. The engineer will be responsible for RTL checks for scan-insertion compatibility, scan-insertion, ATPG pattern generation (compressed and uncompressed), pattern simulation (with and without timing for different corners), and mismatch debug. The position also includes scripting for DFT flow enhancement and automation, MBIST insertion and verification, and IEEE 1149.1 JTAG insertion and verification. Silicon debug and bring-up for both block and top levels are also key responsibilities.
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Job Type
Full-time
Career Level
Senior
Education Level
Associate degree