Physical IC Design Engineer

Broadcom • San Jose, CA

6d • Onsite

About The Position

Broadcom is searching for a Physical Verification PD Engineer to join the Asic Products Division. This position involves working with the advanced nodes to continue driving next generation Artificial Intelligence and Machine Learning ecosystems through our PCIe Switch Products, while leading world class performance, through our Enterprise Products. More specifically, this position will require in-depth knowledge of Foundary rules, DFM and experience in silicon tape-out and respins.

Requirements

• Hands-on experience in running physical verification (LVS,DRC,ERC,PERC)
• Experience in parasitic extraction tools i.e. StarRC, Quantus
• Experience with EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
• Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
• Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience
• Electrical Rule Checking (ERC/PERC): Analyze ESD (Electrostatic Discharge), latch-up, floating gates, and power-domain isolation vulnerabilities
• Density & Fill: Manage automated dummy metal, poly, and diffusion filling strategies to meet local and global density rules
• Yield Enhancement (DFM): Implement Design for Manufacturability fixes, including critical area analysis (CAA), via-doubling, and edge-displacement rules.
• Collaborate with physical design team to resolve critical top-level integration violations
• Experience in scripting languages like Python, Tcl, or Perl
• Excellent verbal and written communication skills
• Must work in person at our San Jose site and no remote work allowed

Nice To Haves

• Bachelors's degree in Electrical Engineering and 8+ years of experience in physical design and verification
• Master's degree in Electrical Engineering and 6+ years of experience in physical design and verification

Responsibilities

• Execution of Chip level Physical Verification & Issue Resolution
• Work on setting up runsets for advance nodes and tool flows
• Manage and guide rules related to top level floorplan, I/O and bump planning
• Resolve physical design issues related to chip integration and assembly
• Provide technical direction on verification methodologies including DRC, LVS, ERC, and PERC
• Develop best practice guidelines for physical verification flows and runtime optimizations

Benefits

• Discretionary annual bonus
• Competitive new hire equity grant
• Annual equity awards
• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave
• Vacation time
• Paid Family Leave
• Other leaves of absence

What This Job Offers

• Job Type: Full-time
• Career Level: Senior