New College Grad - Design Engineer, NVEG

Micron Technology • San Jose, CA

4d • $83,000 - $198,000 • Onsite

About The Position

The Non-Volatile Engineering Group (NVEG) at Micron contributes to the development of memory products that are best-in-class in terms of die size, performance, reliability, and power. Our NVEG organization is dedicated to advancing non-volatile memory technologies such as NAND. Our primary mission is to innovate and develop groundbreaking solutions that improve the performance and reliability of non-volatile memory products. This Design Engineer position will contribute to the development of new memory products by assisting with the overall design, layout, and optimization of datapath circuits for NAND flash memory. This person will help make strategic decisions on major datapath architectural changes influenced by new design specs such as higher speed/lower power. They will assess pros and cons of new architecture and contribute to its implementation. The role will be expected to collaborate with other engineers on technical datapath design projects, participating in the design planning, layout, and validation activities according to project timelines.

Requirements

• A completed BS or MS in Electrical Engineering and 0-2 years of full-time professional experience in semiconductor manufacturing
• Understanding of physical design flows, high-speed IO circuit performance, power and area optimization, and chip architecture/floorplan
• Demonstrated ability of being an active participant in complex design projects and effectively communicating progress and outcomes

Nice To Haves

• PHD in Electrical Engineering and/or a focus on Microelectronics
• Hands-on experience in using AI to improve quality of design and efficiency
• Coursework in/understanding of CMOS BSIM model, CMOS targets for high speed IO operation, and CMOS device reliability

Responsibilities

• Manage major IO/datapath block (e.g. input receiver, serializer, deserializer, clock distribution, equalizer, ZQ calibration, ONFI training features, wave pipeline) to meet specifications and verify functionality and performance
• Model parasitics and review layout regularly and find opportunities of improving area/power
• Communicate with project integration and other functional teams on specifications of major block interfaces
• Communicate with PE to drive silicon experiments and propose and implement fixes for yield improvement and silicon debugging
• Document and review final results with senior engineers and project partners
• Leverage AI and automation to facilitate workflow acceleration and ongoing research

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level