New College Grad - Design Engineer

Micron Technology•San Jose, CA

2d•$86,000 - $173,000

About The Position

Micron Technology develops memory and storage solutions and silicon-to-systems products. The NVE Design Engineer is a core technical individual contributor focused on designing and validating on-chip controllers and mixed-signal circuitry in NAND Flash devices. The position contributes to architecture development and product definition, creates verification strategies and test plans, and carries out subsystem-to-full-chip verification across RTL, firmware, and Verilog environments. The team collaborates globally with design and verification organizations and works closely with Product Engineering, Test, Probe, and Process Integration to improve manufacturing cost, quality, reliability, time-to-market, and customer satisfaction.

Requirements

Bachelor’s degree or Master’s degree in Electrical Engineering or a related field.
Experience contributing to architecture development and product definition, test planning, system integration, and verification for controller and/or mixed-signal circuitry.
Experience developing and supporting verification testbenches and assertions for subsystem and full-chip verification using SystemVerilog, SVA, Verilog, and UVM.
Experience with RTL code coverage and functional coverage analysis to meet coverage goals.
Experience building or supporting automation pipelines or tooling in an engineering environment, such as with Perl and/or Python.

Nice To Haves

Understanding of at least one emulation platform, such as Cadence Palladium, Mentor Veloce, or Synopsys Zebu.
Experience performing emulation FPGA builds for SoC designs and evaluating tradeoffs among build size, emulation speed, and debuggability.
Experience developing new transactors and hybrid emulation models.
Familiarity with model evaluation, dataset creation, feature engineering, and using AI.
Experience working with larger datasets using common Python machine-learning or data libraries.

Responsibilities

Develop and review random-sequence testbench content by analyzing block-level specification documents for new and legacy features.
Build, enhance, and support SVA/SystemVerilog assertion-based verification environments, including UVM testbenches, for subsystem and full-chip Verilog verification.
Execute modeling and simulation workflows using industry-standard simulators, and drive RTL code coverage and functional coverage closure.
Implement, enhance, and support automation tools and workflows to improve design verification efficiency using scripting languages such as Perl and Python.
Develop synthesizable NAND models for FPGA emulation of ASIC controller designs.
Contribute to cross-group communication and standardization.