Design Engineer (7848)

TSMC•San Jose, CA

6d•Onsite

About The Position

Responsible for the Design Rule Check, Layout vs. Schematic checking and fixing all PDV/EMIR/Noise/SigEM violations and errors. You may also do customization and implementation of top clocks and implement timing ECOs on high performance blocks. Specific job duties include: DRC/LVS/ERC/ANTENNA analysis and clean up, Floorplan analysis and congestion solution; Power IR/EM analysis and fix; Signal EM/Noise analysis and fix; Physical verification sign off; Implement ECOs for timing closure; Customized Clock tree structure; May also perform floorplan, place and route.

Requirements

Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field of study
Experience in RTL coding, digital design and testing, physical implementation or design verification
Experience in Perl/TCL language programming
Experience with N16 and below technology
Experience with Chip level integration, and wire editing
Low-power implementation methodology
Experience with Netlist-GDS P&R, signoff task
Experience in block level implementation or chip integration and signoff
Knowledge of major EDA tools/design flows
Knowledge of hardware design including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation