At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a leader in electronics and system design, leveraging over 30 years of computational software expertise. The company’s Intelligent System Design strategy enables creating software, hardware, and IP that turn design concepts into reality. Cadence's customers include the world’s leading companies who deliver extraordinary electronic products across various dynamic market applications such as hyperscale computing, 5G communications, automotive, aerospace, and healthcare. Recognized by Fortune magazine for eight consecutive years, Cadence is one of the 100 Best Companies to Work For. This is a full-time, on-site role for a Post Silicon Electrical Validation Engineer (grade T1) based in San Jose, CA, in the Cadence IP group. The engineer will be responsible for validating the electrical performance of our internal silicon test chips, debugging silicon issues by collaborating with the analog and digital design teams and releasing high quality characterization reports. The role involves collaborating with cross-functional teams to ensure the reliability and functionality of the product. Cadence is at the forefront when it comes to the development of bleeding edge technology SERDES designs such as PCIe Gen7, 224Gbps Ethernet amongst other protocols and joining us gives you a golden opportunity to partner in our progress.
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Job Type
Full-time
Career Level
Entry Level