DDRSS Systems Engineer

Qualcomm•San Diego, CA

33d•$121,800 - $182,600

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. The DDRSS Systems Engineer is responsible for validating, tuning, and optimizing the DDR subsystem across pre-silicon and post-silicon platforms. This role requires close collaboration with design, validation, architecture, and software teams to ensure critical power, performance, reliability, and functionality features are successfully enabled in Qualcomm products. The team is responsible for the development, integration, and validation of low-level DDR subsystem firmware and APIs. Engineers leverage their understanding of system architecture, memory subsystem behavior, and hardware/software interactions to methodically collect and analyze stability, power, performance, and functional data that drive product decisions and optimization efforts. This is a highly cross-functional role requiring a strong foundation in embedded systems, digital design, and system-level debugging. Responsibilities include firmware development in C, validation of firmware across DV environments, emulation platforms, FPGA prototypes, and silicon, as well as post-silicon bring-up and performance characterization activities. The ideal candidate will have a solid understanding of LPDDR protocols, caches, interconnects, and memory controllers. The candidate should be comfortable working across the entire product lifecycle, from design validation through silicon bring-up and production readiness.

Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with a focus on Embedded Systems, Computer Architecture, or VLSI.
2+ years of experience in embedded firmware or low-level software development.
Strong programming skills in C.
Experience with embedded system debugging and hardware/software integration.
Understanding of digital design fundamentals and computer architecture concepts.
Experience using lab equipment and silicon debugging tools to collect and analyze system data.
Familiarity with LPDDR memory interface concepts and protocol fundamentals.

Nice To Haves

Experience with LPDDR4/LPDDR5/LPDDR5X memory protocols, training algorithms, timing parameters, and power management features.
Experience with DDR subsystem validation, characterization, and post-silicon bring-up.
Experience debugging and collecting data from silicon platforms.
Experience developing or maintaining Verilog/SystemVerilog simulation testbenches and validation environments.
Familiarity with memory controllers, caches, coherent interconnects, and SoC architecture.
Experience in performance analysis, power optimization, or system tuning activities.
Familiarity with emulation platforms and FPGA prototyping environments.
Experience with Python, scripting, or automation used for validation and data analysis.

Responsibilities

Develop and maintain low-level firmware and system APIs for DDR subsystem initialization, training, power management, and performance features.
Validate firmware functionality in simulation, emulation, FPGA, and silicon environments.
Analyze and debug system issues spanning hardware, firmware, and software domains.
Collect and interpret stability, performance, power, and reliability data to guide design and product decisions.
Collaborate across design, DV, software, architecture, and product teams to enable and optimize DDR features.
Perform DDR subsystem bring-up and characterization on pre-silicon and post-silicon platforms.
Debug memory subsystem issues involving LPDDR interfaces, caches, interconnects, and memory controllers.
Contribute to the definition and validation of next-generation memory subsystem capabilities and optimizations.