Datacenter & Agentic AI Workload Performance Analysis Engineer

Tenstorrent•Santa Clara, CA

5d•Remote

About The Position

Tenstorrent is seeking a Workload Performance Analysis Engineer to contribute to the performance of their next-generation RISC-V CPUs for datacenter and agentic AI workloads. This role involves bridging hardware and software by bringing real-world applications to RISC-V platforms, characterizing their behavior, and identifying opportunities for improved CPU performance, efficiency, and scalability. The engineer will collaborate with CPU architects, RTL designers, software engineers, and compiler teams to understand workload impact on the CPU and drive architectural enhancements. Responsibilities include reducing large production workloads for performance modeling and correlating simulation results with hardware behavior, directly influencing CPU architecture for cloud, enterprise, and AI workloads. This is a remote position based in North America, and candidates at various experience levels will be considered.

Requirements

PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field, with strong research or industry experience in workload characterization, benchmark development, performance analysis, or simulation.
Deep understanding of CPU architecture and RISC-V, including pipelines, speculative execution, vector/SIMD extensions, memory hierarchies, and performance tradeoffs.
Hands-on experience with performance analysis and simulation tools such as Linux perf, strace, QEMU, or CPU microarchitecture simulators.
Strong programming skills in C/C++, Python, Bash/Shell, and assembly or intrinsic programming, with experience working close to the hardware/software boundary.
Strong understanding of systems software, including operating systems, virtualization, compilers, runtimes, and GNU/RISC-V software ecosystems.

Nice To Haves

Experience connecting software behavior to hardware performance.
Understanding of modern CPU microarchitecture, including superscalar pipelines, speculative execution, memory hierarchies, and vector/SIMD architectures.
Ability to dig into complex workloads, use profiling and simulation data to identify bottlenecks, and turn analysis into actionable recommendations.
Comfort working across hardware and software, from CPU microarchitecture and RTL to operating systems, compilers, runtimes, and applications.
Strong technical communication skills and enjoyment of collaborating with architects, designers, and software engineers on complex performance problems.

Responsibilities

Bring real-world applications onto RISC-V platforms.
Characterize the behavior of applications on RISC-V platforms.
Use workload analysis to uncover opportunities for better CPU performance, efficiency, and scalability.
Work closely with CPU architects, RTL designers, software engineers, and compiler teams to understand how demanding workloads exercise the CPU.
Translate workload insights into architectural improvements.
Reduce large production workloads for performance modeling.
Correlate simulation results with hardware behavior.