CST Application Engineer Intern - Silicon

Cadence Design Systems•San Jose, CA

10d•$29 - $53•Onsite

About The Position

This is a summer 2027 internship opportunity with Cadence Design Systems Customer Success Team (CST) for students currently enrolled in a STEM, electrical engineering, or computer engineering program. The internship focuses on industry-leading electronic design automation (EDA) tools and collaboration with technical experts in silicon design, systems development, and design automation. Interns will gain insight into cutting-edge silicon and systems technologies, learn about the operations of a global technology company, and experience how technical teams solve complex engineering challenges. Cadence is a leader in electronic design with over 35 years of computational software expertise, enabling the creation of advanced electronic products for various dynamic markets.

Requirements

Currently enrolled in a STEM, electrical engineering, or computer engineering program.
Rising senior pursuing a bachelor’s degree in electrical engineering, computer engineering, or another STEM discipline at an accredited university.
Strong communication skills.
Strong presentation skills.
Strong assessment skills.
Strong analytical skills.
Ability to manage multiple complex assignments.

Nice To Haves

Experience with electronic design automation (EDA).
Foundational silicon, package or board design experience.
Experience with AI use cases.

Responsibilities

Participate in a three-month, cohort-based program with hands-on training.
Gain experience in applications supporting system and package design.
Learn digital and analog IC design and simulation.
Engage in physical design and analog layout.
Explore advanced verification and hardware emulation.
Understand the application of artificial intelligence in design disciplines.
Learn from technical experts and application engineers who provide design services, technical sales support, and customer support.