CPU DV Infrastructure Engineer
About The Position
As a CPU DV Infrastructure Engineer specializing in DV methodology and RTL design verification support, you will collaborate closely with design, verification, and CAD leads to define and develop technologies that are vital to our product development. Your role will have a significant impact on team productivity by diagnosing and resolving issues through robust pre-check-in qualification suites, including simulations, static analysis checks, and a variety of miscellaneous scripts. You’ll work hands-on with a broad spectrum of checks and changes across the design repository, actively seeking out details to address problems and improve workflows for the entire worldwide team. In addition to interfacing with cross-functional teams and external vendors, you’ll partner with both CAD and front-end design teams to productize solutions that enable faster, more agile development and ensure the highest standards of quality and reliability are met throughout every stage of the project lifecycle.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Nice To Haves
- Degree in Computer Engineering, Electrical Engineering or Computer Science. BS/BE with 10+ years or MS/ME with 8+ years of experience in Hardware Verification.
- 8+ years of experience in CAD tool/flow development.
- 8+ years of experience with Programming Language such as SystemVerilog, Python, C++.
- 8+ years of experience with scripting and automation environments.
- Strong experience in developing and supporting regression flows/systems, CI/CD, Git workflow, profiling, coverage.
- Passion for building and optimizing tools.
Responsibilities
- Develop and maintain flows, scripts and systems around the RTL and Verification development work cycle like RTL simulators, emulators, coverage, etc.
- Define methodologies and architect flow solutions tied to internal and vendor-based RTL/Verification CAD tools.
- Interact with DV team to diagnose the root cause of complex problems, propose solutions to solve them and guide engineers.
- Collaborate with multiple teams across geographies.
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Senior
