CPU-Core RTL Director
About The Position
Qualcomm is a company of inventors that unlocked 5G and continues to drive the next generation of intelligent computing platforms. Our custom CPU technology powers industry-leading mobile, automotive, XR, AI, and compute products through breakthrough performance and power efficiency. We are seeking an experienced CPU-Core RTL Manager to lead a team of highly skilled CPU RTL engineers responsible for developing industry-leading high-performance, low-power CPU cores. In this role, you will provide technical and organizational leadership across the entire CPU development lifecycle, from early architectural exploration through RTL implementation, verification, physical design convergence, silicon bring-up, and product delivery. The ideal candidate combines deep CPU design expertise with strong people leadership skills. You will drive execution across multiple projects, make informed technical tradeoffs involving power, performance, area, timing, and schedule, and help shape the future direction of Qualcomm's custom CPU roadmap.
Requirements
- Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field.
- 12+ years of experience in CPU RTL design, microarchitecture, or related semiconductor development.
- 3+ years of experience leading engineering teams or large technical projects.
- Strong understanding of modern high-performance CPU architecture and microarchitecture.
- Proven experience delivering complex RTL designs into production silicon.
Nice To Haves
- MS or PhD degree in Computer Engineering, Electrical Engineering, Computer Science, or related discipline.
- Deep expertise in one or more of the following domains: Instruction fetch and branch prediction, Decode and rename, Out-of-order scheduling and execution, Integer and floating-point execution, Vector/SIMD execution, Load-store subsystems, Prefetching and memory hierarchy, MMU and virtualization, Cache and coherency systems, Power management and low-power design.
- Expert knowledge of SystemVerilog and modern RTL development methodologies.
- Strong understanding of timing closure, physical design interactions, power optimization, and silicon implementation.
- Experience leading cross-functional execution across Architecture, DV, PD, DFT, CAD, and Product Engineering organizations.
- Demonstrated ability to make high-impact technical and business tradeoffs under schedule pressure.
- Experience driving methodology, automation, AI-assisted design workflows, and engineering productivity improvements.
- Strong communication and leadership skills with the ability to influence across organizations and executive leadership levels.
Responsibilities
- Lead a team of CPU RTL engineers responsible for the design and delivery of complex CPU subsystems including instruction fetch, decode, branch prediction, scheduling, execution pipelines, memory subsystems, cache hierarchy, power management, and related functionality.
- Partner with CPU architects to translate architectural requirements into scalable and efficient microarchitectural implementations.
- Provide technical direction on microarchitecture, RTL implementation, timing closure, power optimization, verification readiness, and silicon debug.
- Drive high-quality design reviews and ensure design decisions are consistent with long-term CPU roadmap objectives.
- Make critical technical decisions involving power, performance, area, frequency, schedule, and risk tradeoffs.
- Own RTL execution and delivery for one or more CPU projects from concept through silicon.
- Drive milestone planning and execution, including architecture reviews, RTL development, verification readiness, design freezes, tapeout preparation, and post-silicon support.
- Lead bug triage and resolution efforts, ensuring efficient prioritization of functional, performance, power, timing, and methodology issues.
- Evaluate design risks and develop mitigation strategies to maintain project schedules.
- Coordinate cross-functional activities among Architecture, RTL, Verification, Physical Design, Power, DFT, CAD, Emulation, Firmware, and Program Management teams.
- Drive achievement of aggressive performance, power, area, frequency, and product goals.
- Guide teams through complex design tradeoffs involving pipeline depth, structure sizing, speculation mechanisms, clocking strategies, memory hierarchy, and low-power features.
- Review performance analysis, workload data, silicon characterization results, and physical design feedback to identify optimization opportunities.
- Champion design quality through methodology improvements, automation, code health, design reviews, and best practices.
- Recruit, retain, mentor, and develop top engineering talent across multiple experience levels.
- Establish technical growth plans and career development opportunities for team members.
- Foster a culture of accountability, innovation, technical excellence, and collaboration.
- Help define team priorities, resource allocation, and organizational strategy to meet evolving business needs.
- Build strong partnerships across global engineering teams spanning multiple sites and disciplines.
- Support silicon bring-up, performance characterization, power analysis, and post-silicon debug activities.
- Drive root-cause analysis and corrective actions for critical product issues.
- Participate in long-term CPU roadmap planning and technology strategy discussions.
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Senior
