THW Client Co-op
About The Position
This is a 4-month work term position, from August/September to December 2026, within the ASIC IP team. The role involves performing digital ASIC design and verification of Client sub-systems and cores. The Client team is responsible for crafting, developing, and testing the client protocol mapping IP for Ciena’s industry-leading Wavelogic coherent engine Chipsets, which are crucial to Ciena's success. During the coop term, interns will gain knowledge in digital ASIC development, including design and verification environments, prototype development, and development automation. They will be assigned well-defined tasks to contribute to the team, broaden their knowledge, and gain experience in optical networking and digital ASIC development. Responsibilities include RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA-based validation, gaining in-depth knowledge of communications standards (IEEE 802.3, ITU, OIF), and understanding system-wide concepts. The role requires working as a team member responsible for the design and verification of complex digital blocks and subsystems, and implementing/verifying digital designs using System Verilog/UVM.
Requirements
- Good academic standing in a Bachelor’s degree program in Electrical Engineering or Computer Engineering.
- Previous experience with ASIC or FPGA development.
- Knowledge of and experience using System Verilog, Verilog, VHDL and Python.
- Strong verbal and technical writing skills.
- Self-motivated, and the ability to work independently as well as in a team environment.
Nice To Haves
- Knowledge of OTN, Ethernet, and other Optical Networking standards.
- Strong problem solving and debugging skills.
- Experience working in a Linux environment.
Responsibilities
- RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA-based validation.
- Gain in-depth knowledge of many communications standards from IEEE 802.3, ITU, and OIF, as well as understanding system wide concepts.
- Work as a team member that is responsible for the design and verification of complex digital blocks and subsystems.
- Implement and verify digital designs using System Verilog/UVM.
Benefits
- Employee Assistance Program (EAP)
- company-paid holidays
- paid sick leave
- vacation pay
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What This Job Offers
Career Level
Intern
