Chip Lead, Silicon Co-Design Group

NVIDIA•Santa Clara, CA

8d•$196,000 - $368,000

About The Position

The Silicon Co-Design Group (SCG) at NVIDIA operates at the intersection of architecture, design, marketing, operations, and productization, covering the entire lifecycle from early architecture to final product delivery across various markets including Datacenter, Gaming, Robotics, Automotive, and Embedded. We are seeking a Chip Lead to serve as the technical leader for a significant silicon program. This role is distinct from project management or a senior IC position. The Chip Lead is the primary technical point of contact for complex, multi-functional decisions and issues, guiding the program's technical integrity from end-to-end. Responsibilities include leading co-design feature integration, resolving challenging multi-functional bugs, and managing the qualification process, ensuring smoother program execution.

Requirements

BS or MS (or equivalent experience) in Electrical or Computer Engineering.
Over a decade of proven track record in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company.
Experience with multiple shipped silicon products.
12+ years of experience.
Strong end-to-end understanding of SoC and ASIC architecture.
Recognized expertise in at least one subsystem such as HBM, SerDes, power and thermal, or packaging.
Specific examples of silicon-level impact, such as faster bring-up, fewer escapes, yield recovery, or methodology contributions, especially turning ambiguous, multi-team failure modes into root-cause closure with reusable workarounds and write-ups.
A track record of guiding technical decisions across functional boundaries without direct reporting authority.
Ability to translate sophisticated silicon issues into clear options for executive audiences.

Nice To Haves

Prior experience as a Chip Lead, Project Tech Lead, or Principal or Distinguished Engineer on a flagship GPU, AI accelerator, CPU, networking ASIC, or other large SoC.
Patents, conference papers, invited talks, or recognized contributions to silicon validation, post-silicon debug, or co-design integration.
A history of building and sharing technical methodology beyond a single program — reusable playbooks, debug frameworks, or standards adopted by other teams.
Hands-on debug experience with HBM, high-speed I/O, power and thermal, or packaging.
Comfort working through ambiguity with globally distributed teams.
A habit of surfacing the right risks and recommendations to leadership without being asked.
Using AI tools to lift team velocity, not just personal productivity.

Responsibilities

Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs.
Co-lead program-level feature integration from chip to system, identifying and guiding the resolution of inter-function dependencies.
Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging.
Steward the qualification playbook, guiding mitigations for situations where the playbook is insufficient and capturing lessons learned as reusable methodology.
Shape the program’s technical narrative by presenting key risks, trade-offs, and mitigations as decision-ready options for executive leadership.
Mentor Chip Leads on adjacent silicon programs and contribute to SCG-wide methodology through post-mortems and write-ups.
Lead the program’s Critical Debug and SCG Technical Execution forums.
Represent the chip externally, providing early insight into technical risks.