Associate Vice President, Engineering

Marvell Technology•Santa Clara, CA

22h•$242,080 - $362,600

About The Position

This role sits within Marvell’s Connectivity Business Unit and plays a critical role in defining execution strategy, technology roadmap, and customer engagement for industry-leading connectivity products. Marvell is at the heart of the data infrastructure that powers the world. As demand accelerates for bandwidth driven by AI, cloud, and carrier-scale architectures, Marvell is seeking a visionary Associate Vice President (AVP), Engineering to lead the development of next-generation, high-density electrical‑optical connectivity subsystems. In this role, you will bridge advanced CMOS logic, cutting-edge photonics technologies, and innovative multi-chip and packaging solutions to define the future of connectivity. You are not simply leading an organization, you are architecting the ecosystem that will shape the next decade of data center and carrier infrastructure.

Requirements

15+ years of progressive leadership in semiconductor engineering, specifically within high-speed I/O or optical interconnects.
Proven success leading large, complex engineering organizations delivering advanced connectivity or subsystem products.
Deep expertise in Advanced CMOS.
Hands-on experience with Photonics and optical integration.
Proven track record with leading complex subsystem using advanced wafer-to-wafer or die-to-wafer packaging
Demonstrated ability to manage relationships with top-tier silicon foundries and OSAT partners.
Experience leading high-level technical discussions with hyper-scaler and enterprise-level customers.
M.S. or Ph.D. in Electrical Engineering, Physics, or a related field.

Nice To Haves

Photonics, silicon photonics, or optical interconnect experience is highly desirable

Responsibilities

Build, mentor, and scale a world-class engineering organization focused on end-to-end electrical-optical subsystem development.
Foster a culture of innovation, accountability, and execution excellence while attracting and retaining top-tier engineering talent.
Partner closely with the Connectivity leadership team and executive peers to align engineering strategy with business and product priorities.
Define and execute long-term engineering and technology roadmaps spanning advanced CMOS nodes, multi-chip architectures, and electrical‑optical I/O subsystems.
Identify and execute on advanced CMOS nodes, optical technologies, and next-gen I/O architectures to maintain Marvell's competitive edge.
Anticipate architectural shifts in data center connectivity, including transitions.
Serve as the primary technical interface for strategic customers, foundry partners, and Tier-1 vendors to ensure seamless integration and product delivery.
Lead high‑level technical discussions to ensure seamless integration, differentiation, and successful product delivery.
Define and drive advanced packaging flows (2.5D/3D IC, Co-Packaged Optics) and identify key supply chain partners to scale production.
Own subsystem‑level integration using wafer‑to‑wafer, die‑to‑wafer, and chip‑on‑wafer approaches.
Ensure robust design‑to‑manufacturing flows and scalable production readiness.
Lead the design of high-density I/O solutions that optimize for power, latency, and thermal efficiency in extreme-scale computing environments.
Guide teams through the full lifecycle - from architecture and design through NPI and high‑volume manufacturing.
Own departmental planning, budgets, resource allocation, and risk mitigation strategies.
Ensure programs are delivered on time, at target performance, and at scale, while navigating ambiguity and change.