ASIC Technical Lead

Synchron Inc.•San Diego, CA

5d•$180,000 - $220,000

About The Position

Synchron is developing a high-channel-count neural recording ASIC in partnership with an external IC design house, and we are looking for an experienced engineer to own the chip’s technical delivery. Although our partner owns design, simulation, test, and fabrication, this role is accountable for the chip meeting spec and shipping - including catching problems when the partner's work doesn't. This role is the internal technical authority on our cutting-edge neural recording chip: the person technically fluent enough to hold our partner to an airtight specification, independently judge whether their design and simulation work is sound, and gate the program at every major decision point (architecture review, pre-tapeout sign-off, and post-silicon disposition). You're not doing the partner's design work; you're making sure it's correct, on-spec, and defensible. You will have been through at least one ASIC tapeout before (ideally several) so you know firsthand what separates a design review that catches real problems from one that rubber-stamps a partner's summary slide. You hold yourself and others to a high standard and have a proven track record of successfully delivering silicon.

Requirements

B.S. or M.S. in Electrical Engineering (or equivalent) with a silicon design emphasis.
5+ years of experience in ASIC/SoC design and development, with at least one full ASIC development cycle from concept to silicon.
Strong analog or mixed-signal IC design or verification background; comfortable reading and critiquing someone else's schematics and simulations, not only producing your own.
Working fluency with SPICE/Cadence-class simulation review, DRC/LVS, and DFT concepts.
Experience working with an external design partner, foundry, or fab — you understand where partner incentives and program incentives can diverge, and how to write a spec that closes those gaps.

Nice To Haves

experience in a regulated medical device environment (design controls, DHF, 510(k)/PMA) or with implantable-class electronics.

Responsibilities

ASIC requirements and specification: author and maintain the versioned, traceable requirements and specification document that is the single source of truth between us and the design partner.
Design & architecture reviews: run technical reviews with the partner at each gate — block-level, top-level, pre-tapeout — and independently assess their schematics, netlists, and simulation results rather than accepting a summary.
Simulation & sign-off: review SPICE/Cadence simulation results, DRC/LVS, and DFT plans; own the tapeout readiness checklist and make the go/no-go call.
Risk register: track and own design-level risks — process corners, matching, noise budget, power budget across the full channel count — and drive them to closure.
First-silicon bring-up: partner with the AFE Test & Integration Engineer during bring-up; when results are out of spec, lead root-cause to determine whether it's a test artifact, a marginal corner, or a real silicon bug.
Respin leadership: if a respin is required, lead the design review of the fix and the re-verification plan.
Sustaining & roadmap: once qualified, own engineering change orders, risk file / FMEA updates from field or test data, and the specification for any next-generation chip (higher channel count, lower power, new features).