ASIC Power Manager, ML Accelerators

Google•Sunnyvale, CA

4d•$192,000 - $279,000

About The Position

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Power Design Manager within Google's silicon team, you will help deliver solutions that have a substantive impact on the technical infrastructure that enables Google. You will provide technical leadership to a group of power design engineers in an innovative and fast-paced environment, with a focus on ASIC power architecture, design and project execution. You will own and drive complex technical projects from the concept/planning stage through execution and closure. You will bring out the best in your team to deliver designs that work for the first time with optimal power. You will bring your knowledge and experience in large SoC power architecture and design, ability to work with IP and chip vendors and manufacturers, and ability to work across organizational boundaries to identify the right people to provide technical input and execution to deliver SoC-centric products that are key to Google's computing infrastructure. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits Learn more about benefits at Google [https://www.google.com/about/careers/applications/benefits/].

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience with ASIC or SoC design.
Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
5 years of experience managing mid-sized ASIC/SOC design teams with focus on power design and optimization.
Experience defining and implementing chip-wide power management architectures and designs.
Experience in power modeling, measurement, and correlation across the pre- and post-silicon phases.
Understanding of modern power and thermal management techniques at both the silicon and system levels (including Dynamic Voltage and Frequency Scaling (DVFS), Turboing, Thermal Management, and System-Level Tradeoffs).
Ability to solve open-ended power and performance problems under ambiguity.

Responsibilities

Manage a power design team responsible for power architecture, power optimization and system power integration.
Lead an experienced team, define the processes, methods and tools to continuously improve the power efficiency of the TPU designs.
Contribute to design power modeling and drive convergence to power targets.
Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
Define best practices and methodologies to achieve low-power RTL designs.
Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.