ASIC High Speed AMS Technical Leader
About The Position
The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Build the optical backbone of the AI revolution. As our High-Speed Analog/Mixed-Signal Design Engineer, you will directly lead the electrical specifications, custom circuit design, and verification strategies for Cisco’s next-generation 800G, 1.6T, and beyond silicon photonics modules. Operating within our best-in-class Silicon Photonics team, you will own the end-to-end development cycle for 100G/200G/400G per Lambda driver integrated circuits that seamlessly integrate with Cisco's core routing, switching, and datacenter platforms. Your technical leadership will span critical execution phases from concept to production: Datapath & Control Ownership: Author high-performance mixed-signal datapath and low-speed control circuits for both receive and transmit paths—including photonic modulator drivers, serializers, PLLs, and TIAs—while rigorously optimizing for power, performance, testability, and cost. Full-Chip Architecture & Integration: Drive full-chip electrical specifications and comprehensive verification test plans, coordinating tightly across electrical, optical, and product architecture teams. Bring-Up & Yield Enhancement: Debug complex silicon and system-level bottlenecks hands-on during lab validation and bring-up phases to drive yield enhancements and failure analysis. Technical Leadership & Mentoring: Guide and mentor analog, digital, and validation engineers, elevating our team’s engineering excellence across next-gen data center architectures.
Requirements
- Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of high-speed AMS design experience
- Demonstrated expertise in high-speed optical transceiver design (modulator drivers, TIA, CDR, PLLs, ADC/DAC) and proficiency with industry standard tools (Cadence Virtuoso, Spectre, Caliber, SystemVerilog, Verilog-AMS)
- Demonstrated ability to lead design teams through full tapeout cycle, making critical decisions with limited data and delivering successful silicon products
- Proficiency in Python or C for design automation, scripting, and analytical tools
Nice To Haves
- 10-15 years of analog/mixed signal circuit design experience
- Experience with silicon photonics driver ICs and direct-detect optical module architectures
- Strong understanding of silicon photonics, optical subsystems, MSA standards (QSFP/QSFP-DD), and IEEE 802.3 specifications
- Expertise in multiple high-speed PHYs, protocols and subsystems (SerDes 112Gbps/224Gbps PAM4, Ethernet, UCIE, clock and data recovery systems, PLLs, ADC/DAC circuits)
- Demonstrated experience in design for testability (DFT) and test methodology development for large mixed-signal designs
- Proven experience with lab instrumentation (digital communication analyzers, real-time scopes, BERTs), SI/PI and test fixture/PCB
- Familiarity with optical sub-component models (photodiodes, modulators) and Verilog-A modeling for AMS simulations
- Strong collaborator and teammate with the ability to work across teams in multiple sites
Responsibilities
- Author high-performance mixed-signal datapath and low-speed control circuits for both receive and transmit paths—including photonic modulator drivers, serializers, PLLs, and TIAs—while rigorously optimizing for power, performance, testability, and cost.
- Drive full-chip electrical specifications and comprehensive verification test plans, coordinating tightly across electrical, optical, and product architecture teams.
- Debug complex silicon and system-level bottlenecks hands-on during lab validation and bring-up phases to drive yield enhancements and failure analysis.
- Guide and mentor analog, digital, and validation engineers, elevating our team’s engineering excellence across next-gen data center architectures.
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- grants of Cisco restricted stock units
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year (non-exempt)
- flexible vacation time off program (exempt)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (for non-sales roles)
- performance-based incentive pay (for sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Senior
