ASIC/FPGA Verification Engineer IV

Lockheed Martin•Denver, CA

1d•Onsite

About The Position

Join Our Team as a ASIC/FPGA Verification Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment. This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in Sunnyvale CA or Denver or Highlands Ranch CO. You will be working a flexible 9x80 schedule in the office full-time. The Silicon Solutions team of Lockheed Martin Space is building the best ASIC/FPGA team in the world, and are seeking a highly talented and motivated ASIC & FPGA Verification Engineer who has a passion for microchip design and space. You will be working at the Supplier site in Cambridge MA.

Requirements

UVM expertise
SystemVerilog and VHDL mastery
Independently minded and well organized engineer, comfortable in laboratory digital environments, and able to respond and interact with a dynamic fast-moving team.
5+ years professional FPGA verification experience.
Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.
Experience in the verification of FPGA and/or ASIC devices.
Experience with modern verification methodologies such as UVM, OVM or VMM.
HDL programming experience with VHDL, Verilog, and/or SystemVerilog.
US Citizenship is required.
Must be able to obtain and maintain a DoD Secret clearance.

Nice To Haves

Knowledge of space-grade/qualified FPGAs
Experience or knowledge of MS Project, JIRA.
Knowledge of Python or other scripting languages
Experience designing with AMD Versal, Microchip RTG4 FPGAs.
Lab testing experience

Responsibilities

Work with low SWaP, radiation hardened, space rated devices.
Perform all aspects of ASIC and FPGA verification through the lifecycle from initial requirements capture through architecture, design, analysis, simulations and test in a Linux-based high-performance computing environment.
Devise a unique verification plan for a given design.
Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.
Document verification plan and results.
Support technical reviews and present to internal and external stakeholders.
Interface with an independent verification team who will be working in parallel, verifying the design.
Work with an independent verification team to resolve bugs found in the design.