ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)

Teradyne • North Reading, MA

2d • $98,700 - $157,900 • Onsite

About The Position

Our Logic Design Engineering (LDE) team is seeking a Digital Logic Verification Engineer, preferably with additional experience in FPGA design. The primary focus of this role is FPGA verification, working closely with cross‑functional teams to deliver high‑quality, robust designs.

Requirements

• 3+ years of professional experience in digital logic verification or related roles
• Experience with Cadence Xcelium or other industry‑standard simulators
• Strong experience with System Verilog and Universal Verification Methodology (UVM)
• Working knowledge of common IP protocols (e.g., SPI, AXI, DDR)
• Experience with RTL design using Verilog HDL
• Familiarity with System Verilog assertion‑based verification methodologies
• Experience working within CI/CD development flows

Nice To Haves

• additional experience in FPGA design

Responsibilities

• Review design requirements and specifications
• Write and review verification plans
• Develop testbench architecture and implementation
• Create reference models
• Write System Verilog tests and develop UVM environments; perform debug
• Collect, merge, and close functional and code coverage
• Manage bugs and issues using a tracking tool
• Collaborate closely with logic designers
• Communicate technical status and risks to the team leader

Benefits

• medical
• dental
• vision
• Flexible Spending Accounts
• retirement savings plans
• life and disability insurance
• paid vacation & holidays
• tuition assistance programs

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed