FPGA/ASIC Design Engineer

Innova Solutions•Camden, NJ

9h•Onsite

About The Position

A client of Innova Solutions is immediately hiring an FPGA/ASIC Design Engineer. This is a full-time contract position with a duration of 12 months, with the possibility of contract to hire. The role is based onsite in Camden, NJ. As an FPGA/ASIC Design Engineer, you will be responsible for the architecture, implementation, and verification/validation through Software integration test, for the delivery of complex FPGAs and/or ASICs systems. This is a key, high impact, high visibility role in the organization to ensure robust quality and delivery of Communication products for National Security. You will develop architecture for the implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL) with high-speed protocols NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) and/or ASICs. Additionally, you will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux. You will deploy state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), Catapult (HLS).

Requirements

At least 3-years’ experience with proven track record of implementing complex algorithms targeting ASIC/FPGAs.
Proficiency in VHDL and FPGA design/debug Xilinx FPGA / Vivado.
Excellent Analytical/Debug skills.
High Level Synthesis (HLS) with Vivado, Embedded SW C++ (OOP) and System Verilog Assertions (SVA).
Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet).
Active DoD Secret Security Clearance.

Nice To Haves

VHDL Experience Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado.
Hands on multiple complex designs arch/design/verification/Synthesis/STA Big Plus.
Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
Mentor EDA CDC/Lint/AC/RDC.
Master of Science in Electrical Engineering or Computer Science preferred.
Bachelor of Science in Electrical Engineering or Computer Science or equivalent.

Responsibilities

Architecture, implementation, verification/validation through Software integration test, for delivery of complex FPGAs AND/OR ASICs systems.
Develop architecture for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL) with high-speed protocols NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) AND/OR ASICs.
Writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions.
Writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
Deployed state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), Catapult (HLS).