ASIC & FPGA Design Engineer

Geologics•Houston, TX

8h•Onsite

About The Position

This role involves working with low SWaP (Size, Weight, and Power), radiation-hardened, space-rated devices. The engineer will develop RTL/VHDL code, scripts, and supporting materials for FPGA design, including self-test designer-level testbenches. Responsibilities include debugging and simulating circuitware using Xilinx development tools, delivering RTL source code changes, test data, and documentation. The engineer will collaborate with systems and design engineers on concept of operations and design requirements, and support verification engineers with FPGA design verification. Additionally, the role requires contributing to design documentation per approved processes, attending team meetings and reviews, and maintaining data and drawings on secure internal networks following security guidance.

Requirements

Experience synthesizing and building designs targeting Microchip and Xilinx/AMD FPGAs, including UltraScale+, RT PolarFire, Versal, and RTG4.
Proficiency with Libero, Vivado, and Synopsys tools across simulation, lint/CDC, and synthesis workflows.
Design experience in Verilog, SystemVerilog, and VHDL.
Experience debugging FPGA designs both in simulation and in the lab, including working across teams to resolve issues.
Experience with SpaceWire interfaces.
Experience using Python for scripting and design support.
Ability to ramp up quickly on existing designs and interpret requirements documentation.
Willingness to contribute to milestone review materials — including requirements documentation, analysis, and presentations.
B.S. or higher in Electrical Engineering or a related field, or equivalent experience.
Must possess 9+ years of related experience.

Nice To Haves

Ability to Obtain Secret Clearance. Not needed to start.

Responsibilities

Develop RTL/VHDL code, scripts, and supporting materials for FPGA design, including self-test designer-level testbenches.
Debug and simulate circuitware using Xilinx development tools.
Deliver RTL source code changes, test data, and documentation.
Collaborate with systems and design engineers on concept of operations and design requirements.
Support verification engineers with FPGA design verification.
Contribute to design documentation per approved processes.
Attend team meetings and reviews as needed.
Keep all data and drawings on secure internal networks, following provided security guidance.