ASIC & FPGA Design Engineer Sr.

Lockheed Martin•Orlando, FL

4d•Hybrid

About The Position

You will be the Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team supporting the Next Generation Short Range Interceptor (NGSRI). Our team creates the digital heart beats—ASICs and FPGAs—that enable precision engagement aerospace and defense systems for the United States and allied forces. As the Senior ASIC & FPGA Design Engineer you will own the architecture, development, verification, and delivery of the Datalink FPGA that powers the NGSRI. You’ll translate system level performance, safety, and reliability goals into robust, production ready logic while mentoring junior talent and collaborating across disciplines.

Requirements

Bachelor of Science degree in Electrical Engineering or a closely related STEM field from an accredited university; Master’s degree preferred
Minimum 3 years of professional experience with FPGA design and simulation verification or a related discipline
Proficiency in HDL programming with VHDL, Verilog, and/or SystemVerilog
Experience with Xilinx/AMD toolsets (Vivado, Vitis, Vitis HLS) and UltraScale design methodology
Experience with FPGA simulation tools such as Synopsys VCS
Strong understanding of digital design principles, including timing analysis, clock domain crossing, and signal integrity
Experience with high-speed interfaces such as AXI, Ethernet, TCP/IP, PCIe, and serial protocols
Practical laboratory debug experience with high-speed oscilloscopes, spectrum analyzers, and signal generators
Familiarity with Synopsys EDA tools
Must be a US Citizen; must possess or be able to obtain a DoD Secret clearance

Nice To Haves

LM/MFC design experience and missile program experience
Experience with DSP, radios, and digital communications for datalink and telemetry uses on a small form factor
Experienced on Xilinx SOC platforms and analog devices transceivers
Capable of writing Verilog, Simulink for HDL coder, and C/C++
Experience with MAthworks/ HDL Coder
Experience with digital Communication system
Strong communication, collaboration, and presentation abilities
Active DoD Secret or Top Secret clearance

Responsibilities

Defining architecture and design specifications for programmable logic components; writing clean, well documented RTL in VHDL/Verilog/SystemVerilog.
Developing synthesis, place and route, and timing closure strategies to achieve deterministic operation on target FPGA families.
Building comprehensive test plans, simulation models, and verification environments (UVM, SystemC, Python based testbenches) to prove functional correctness and timing margins.
Leading hardware in the loop (HIL) testing, board level debugging, and subsystem integration.
Performing timing analysis, power budgeting, and resource utilization studies to guide device selection and optimize FPGA utilization.
Managing configuration control with GitLab (or equivalent), maintaining version controlled repositories, and ensuring full traceability of all artifacts.
Producing complete design packages—specifications, test plans, verification reports, and release documentation—meeting aerospace standards and Lockheed Martin command media requirements.
Collaborating with systems, software, mechanical, test, manufacturing, and quality teams to keep the program on schedule and within performance envelopes.
Mentoring junior engineers, championing best practices in FPGA/ASIC development, verification, and configuration management.