ASIC Engineer, Infrastructure Silicon Validation

Meta•Sunnyvale, CA

18d•$264,000 - $341,000

About The Position

Meta's Infrastructure Silicon team designs and deploys custom silicon for the compute, networking, and storage infrastructure that supports its global data centers. The principal-level ASIC Engineer will define and drive end-to-end validation strategy for custom ASICs, including compute accelerators, network ASICs, and storage controllers. The role shapes silicon bring-up, functional validation, and post-silicon debug methodologies to help ensure reliability and performance for hyperscale infrastructure deployments. The engineer will set validation direction across multiple program generations, lead bring-up and failure analysis, build scalable validation frameworks, and establish program readiness criteria from tape-out through production qualification. The role also involves influencing future ASIC design through post-silicon feedback, mentoring engineers, and representing validation in cross-functional and external technical discussions.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
15+ years of experience in post-silicon validation, silicon bring-up, or ASIC characterization for high-complexity custom ASICs in compute, networking, or storage domains.
Experience defining and executing validation strategies for high-speed interfaces such as PCIe, DDR, HBM, Ethernet, or custom SerDes links at multi-gigabit data rates.
Experience with DFT methodologies, including scan, BIST, JTAG, and boundary scan, as applied to post-silicon debug and production test coverage.
Experience leading multi-generational silicon validation programs from tape-out through production qualification in a hyperscale or high-volume manufacturing environment.
Experience developing automated silicon characterization and regression frameworks using scripting languages such as Python, Tcl, or equivalent.

Nice To Haves

Background developing silicon validation IP or reusable test infrastructure spanning multiple ASIC programs or product families.
Experience collaborating with foundry partners on process-related failure analysis, yield improvement, and reliability qualification for advanced process nodes.
Familiarity with formal verification, emulation platforms, or pre-silicon simulation environments and their correlation to post-silicon validation outcomes.
Experience validating custom silicon deployed in large-scale data center infrastructure, including thermal, power integrity, and signal integrity characterization under production workloads.

Responsibilities

Define and own the long-term post-silicon validation strategy for custom infrastructure ASICs across compute accelerators, network ASICs, and storage controllers and multiple program generations.
Architect scalable validation frameworks and test methodologies for functional verification, performance characterization, and reliability qualification in data center environments.
Lead silicon bring-up, including power-on sequencing, clock and reset validation, memory interface bring-up, and high-speed SerDes link characterization.
Drive root-cause analysis and debug of complex silicon failures using lab instrumentation, logic analyzers, oscilloscopes, and custom diagnostic firmware.
Collaborate with pre-silicon design and verification teams to incorporate testability requirements, DFT coverage, and scan chain integrity early in the design cycle.
Partner with system software, firmware, and platform engineering teams to develop validation infrastructure, diagnostic tools, and automated test suites for silicon characterization.
Establish validation milestones, risk assessments, and readiness criteria for tape-out, first silicon, and production qualification gates across concurrent programs.
Influence silicon architecture and design decisions through post-silicon feedback that informs future ASIC generations and improves first-pass silicon success rates.
Mentor engineers across the validation organization and promote best practices in post-silicon debug, test automation, and characterization methodology.
Represent the silicon validation organization in cross-functional technical reviews, executive program readiness discussions, and engagements with foundry and IP vendors.