ASIC Engineer - Early Career

Blue Origin • Bay Area, WA

9d

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! We are collaborators, doers, and problem-solvers who are relentlessly committed to a culture of safety. This position will directly impact the history of space exploration and will require your commitment and detailed attention towards safe and repeatable space flight. Join us in lowering the cost of access to space and enabling Blue Origin’s vision of millions of people living and working in space to benefit Earth. Multiple positions available across our Business Units. You will be matched with an appropriate engineering team based on your skillset and experience and our current business needs. Applications will be reviewed on a rolling basis. We prioritize placing early career engineers in locations where they can be co-located with their team and the relevant hardware they support. Please indicate in the application where you would be willing to be located.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or related technical field (completed or in final year)
• Coursework or project experience with Verilog/SystemVerilog RTL design or verification
• Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing)
• Familiarity with basic verification concepts (testbenches, simulation, coverage)
• Strong problem-solving skills and attention to detail
• Effective communication and ability to work in a collaborative team environment

Nice To Haves

• Academic or internship experience with SystemVerilog/UVM
• Exposure to scripting languages (Python, Perl, Tcl) for automation/tooling
• Coursework or projects involving communications systems, DSP, or FPGA design
• Familiarity with common EDA tools (e.g., VCS, Xcelium, Questa, formal tools)
• Understanding of computer architecture fundamentals (CPUs, bus protocols like AXI)
• Personal projects, capstone work, or research involving digital design/verification (e.g., GitHub repos, senior design projects)

Responsibilities

• Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs
• Support module-level and subsystem-level verification using SystemVerilog/UVM
• Write test plans and functional coverage definitions under guidance from senior team members
• Assist with CDC/RDC/LINT checks and clean-up
• Participate in code coverage and functional coverage closure activities
• Help develop assertions, protocol monitors, and scoreboards for testbenches
• Support integration and verification of external IP (e.g., bus fabrics, standard interfaces)
• Learn and apply industry-standard verification methodologies (UVM, formal verification basics)
• Debug RTL and testbench issues with guidance from senior engineers
• Document design intent, verification results, and test coverage

Benefits

• Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level