Sr. / Staff ASIC Digital Design Engineer

SK hynix•San Jose, CA

About The Position

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape. We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing. Position Overview We are looking for a highly motivated ASIC Digital Design engineer with expertise in DFT, Synthesis, Power, and Timing analysis to support our hardware engineering team. As a member of ASIC implementation team, you are expected to drive automated flows to streamline sign-off for multiple teams, and ensure high quality deliveries to achieve tapeout milestones.

Requirements

Demonstrate expertise in multiple Tapeouts
Extensive experience in frontend tools such as PT, DC, VCLP, Formality, LEC, PrimeClosure, PrimePower, VCS, VC-spyglass-dft, Tetramax, Tessent, etc.
Low-Power Design flow with UPF.
Familiarity with UNIX/Linux environments, tcl/perl/python/shell scripting
Strong attention to detail and ability to follow structured workflows.
Bachelors in Engineering and 8+ years of related experience, or Masters degree in Engineering and 6+ years of related experience.

Nice To Haves

AI-assisted flow experience is a plus.
Direct experience taping out designs in advanced semiconductor technology nodes (e.g., 7nm, 5nm, or below).
Familiarity with voltage drop analysis.
Experience with ATE bring-up, failure analysis and yield improvement.
Experience with CDC/RDC/Lint checks.
Experience with floorplan / timing-driven placement / clock-tree synthesis / Xtalk analysis.

Responsibilities

Responsible for top-level DFT planning and integration.
Managing the ATPG (Automatic Test Pattern Generation) and ATE (Automated Test Equipment) interface, including ATE bring-up and failure analysis.
Driving test time reduction strategies.
Leading Synthesis , Formality, Timing checks, provide guidance, interface with RTL design team for quality RTL delivery.
Full chip and Block constraints development & STA;
Working independently with the PNR & RTL design team on Physical implementation & Power-intent requirements.
Power & IR analysis; implementing DFT across multi-power domain designs.
Troubleshooting Synthesis / Timing / DFT / Power related issues, continuously driving flow improvements.
Help maintain scripts, documentation, IP DK, and SoC signoff checklists.