ASIC Digital Design Engineer, Architect-18709

Synopsys•Austin, TX

32d•$181,000 - $271,000•Onsite

About The Position

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are: An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. You can define and executing a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.

Requirements

BSEE or BSCE +12 years or an advanced degree and +10 years industry experience
Extensive experience in ASIC RTL design.
In-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications.
Proficiency in advanced digital design tools and methodologies.
Strong problem-solving skills and the ability to work independently.
Excellent communication skills for effective collaboration with diverse teams.

Nice To Haves

A visionary leader with a strategic mindset.
A mentor who fosters talent and encourages innovation.
A proactive problem solver who thrives in complex environments.
An effective communicator with the ability to convey technical concepts to a broad audience.
A team player who values collaboration and diversity.

Responsibilities

Defining and developing ASIC RTL design and verification at both chip and block levels.
Creating and executing design plans for complex digital designs, particularly focusing on DDR, PCIe, CXL, UAL, UCIe IO protocols.
Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.
Utilizing advanced design and verification methodologies and tools to achieve high-quality results.
Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.
Communicating with internal and external stakeholders to align on project goals and deliverables.