ASIC Design Engineer - New College Grad 2027

NVIDIA•Us, CA

23h

About The Position

Our work at NVIDIA is dedicated towards a computing model focused on visual and AI computing. For two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics, with our invention of the GPU. The GPU has also shown to be spectacularly effective at solving some of the most complex problems in computer science. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots and self-driving cars that can perceive and understand the world. We are looking to grow our company and teams with the smartest people in the world and there has never been a more exciting time to join our team! We are seeking an ASIC Design Engineer - New College Graduate to implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Requirements

Pursuing or recently completed a BS or MS in Electrical Engineering, Computer Engineering or Computer Science or related field or equivalent experience
Knowledge of micro-architecture and RTL development (Verilog).
Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic is required.
Strong interpersonal skills and an excellent teammate.

Nice To Haves

Strong C/C++, Python or Perl skills.
Good debugging and analytical skills.
Experience with arbiters, scheduling, synchronization & bus protocols, interconnect networks, caches

Responsibilities

Implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
Analyze architectural trade-offs based on features, performance requirements and system limitations.
Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design.
Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.
Work on a broad list of IPs such as GPU's work scheduler, time distribution system, interrupt controllers, and DMA engines.
Architect features to help silicon debug and support post-silicon validation activities.