The ASIC Design Engineer Intern will help design and integrate next-generation silicon for Cisco’s core networking products, contributing to phases of the ASIC design lifecycle and collaborating with cross-functional teams to support robust, high-performance solutions. The role includes implementing Verilog RTL, supporting chip integration and timing analysis, developing functional coverage, debugging design issues, and helping with post-silicon validation. This posting advertises potential future opportunities; the exact role may not be open currently, and applications are accepted until further notice.
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Career Level
Intern
Education Level
Associate degree