ASIC Clocks Design Engineer - New College Grad 2026

NVIDIA•Austin, TX

1d•$100,000 - $189,750

About The Position

Our team crafts all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab.

Requirements

Bachelor's degree or higher in Electrical Engineering (or equivalent experience).
Understanding of logic optimization techniques and PPA trade-offs.
Shown ability to collaborate with multiple teams.
Experience in RTL design (Verilog), verification and logic synthesis.
Strong coding skills in Python or other industry-standard scripting languages.

Nice To Haves

Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.
Implementing on-chip clocking networks is a bonus.

Responsibilities

Architecting the clock domain to satisfy functional, physical and testing design requirements.
Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints.
Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking.
Deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams.
Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.