Applications Engineer

Lattice Semiconductor•Hillsboro, OR

4d•Onsite

About The Position

As a technical leader, provide applications support for DDR (e.g., DDR4 / DDR5 / LPDDR, High‑Speed IOs, and interfaces (e.g., PCIe, SerDes, Ethernet, ). Support customer design‑ins, including interface configuration, signal integrity guidance, board‑level considerations, and system optimization. Analyze issues using oscilloscopes, logic analyzers, protocol analyzers, and BERTs; provide clear root cause and corrective action plans. Provide customer feedback to internal teams to influence product requirements, feature prioritization, and roadmap decisions. Support FAE, sales, and marketing teams with technical guidance, value propositions, and contribute to best practices for DDR and HSIO system design and debug. Stay current on JEDEC standards, protocol specifications, and industry trends related to memory and high‑speed interfaces.

Requirements

Solid understanding of DDR memory architectures and protocols (DDR4/DDR5 and/or LPDDR).
Hands on experience supporting silicon products (SoCs, PHYs, controllers, memory interfaces).
Strong knowledge of High Speed Serial and Parallel IO fundamentals, including: Signal integrity (SI), timing, jitter, noise, and power integrity (PI), Eye diagrams, timing budgets, and channel modeling
Experience with high speed lab equipment (oscilloscopes, protocol analyzers, BERTs).
Familiarity with PCB design considerations for high speed interfaces (stack ups, routing, termination).
Ability to explain complex technical topics clearly to both technical and non technical audiences.
Strong problem solving and analytical mindset.
Familiarity with memory training, calibration flows, and PHY tuning.

Responsibilities

Provide applications support for DDR (e.g., DDR4 / DDR5 / LPDDR, High‑Speed IOs, and interfaces (e.g., PCIe, SerDes, Ethernet, )
Support customer design‑ins, including interface configuration, signal integrity guidance, board‑level considerations, and system optimization.
Analyze issues using oscilloscopes, logic analyzers, protocol analyzers, and BERTs; provide clear root cause and corrective action plans.
Provide customer feedback to internal teams to influence product requirements, feature prioritization, and roadmap decisions.
Support FAE, sales, and marketing teams with technical guidance, value propositions, and contribute to best practices for DDR and HSIO system design and debug.
Stay current on JEDEC standards, protocol specifications, and industry trends related to memory and high‑speed interfaces.