Analog Mixed Signal IC Design Principal Engineer

Marvell Technology • Toronto, ON

51d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. This is an existing vacancy. Your Team, Your Impact As an Analog IC Design Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Data Center, Storage, Security, and Networking. You’ll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects. What You Can Expect The candidate will be leading the high-speed and high performance SerDes development in advanced technology nodes, 5nm, 3nm, 2nm and beyond. Design IP that includes but not limited to 224G/112G/56G PAM4; 32G PAM2; Die-to-Die High Speed Interconnect; System PLL IPs; General Analog Circuits Participate the SerDes architecture development with the DSP, Analog and Digital design teams. Provide the instructions to the layout engineers. Working with the AE for the IP characterization and validation plan. Supporting IP Lab characterization and debugging. Product and customer supporting.

Requirements

• Bachelor’s degree in Electrical Engineering and 12+ years of related professional experience.
• Master’s degree with 8+ years of experience and/or PhD in Electrical Engineering with 5+ years of experience
• Experience in high speed analog mixed signal design in 7nm and below for TSMC process.
• Demonstrable knowledge of high performance SerDes development
• Demonstrable team player and works well in a collaborative environment
• Project leading and SOC support is preferred

Nice To Haves

• PAM4 112G and 224G SerDes Design experience highly desired
• D2D and DDR experience a plus
• Strives to make others better

Responsibilities

• Leading the high-speed and high performance SerDes development in advanced technology nodes, 5nm, 3nm, 2nm and beyond.
• Design IP that includes but not limited to 224G/112G/56G PAM4; 32G PAM2; Die-to-Die High Speed Interconnect; System PLL IPs; General Analog Circuits
• Participate the SerDes architecture development with the DSP, Analog and Digital design teams.
• Provide the instructions to the layout engineers.
• Working with the AE for the IP characterization and validation plan.
• Supporting IP Lab characterization and debugging.
• Product and customer supporting.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Number of Employees: 1,001-5,000 employees